1. Field of the Invention
The present invention generally relates to an antifuse via structure, and more particularly to a method of a metal via antifuse used in field programmable gate array (FPGA) for forming an antifuse via structure.
2. Description of the Prior Art
Referring to FIG. 1, a structure of conventional via antifuse used in FPGAs. The conventional antifuse via structure comprises a substrate 100 having a first conductive wire 102 therein. A first dielectric layer 104 covers on the substrate 100 and first conductive wire 102. Then, a photoresist layer (not shown in FIG.) is formed on the first dielectric layer 104, and performing an etching process to the first dielectric layer to expose partial conductive wire 102 to form a via open 106 in the first dielectric layer 104. Then, a first conductive layer is deposited on the first dielectric layer 104 and to fill the via open 106, wherein the via open 106 is on the first conductive wire 102. Then, a polishing process such as chemical mechanical polishing (CMP) is performed to remove the excess first conductive layer to form a conductive plug 108.
Then, referring to FIG. 2, a buffer layer 110 is deposited before the formation of the first electrode 112. Next, another CMP process is performed to the buffer layer 108 to remove portion of the buffer layer 110 on the surface of the conductive plug 108 to expose the portion of the conductive plug 108. Then, a first electrode 112 of the capacitor is deposited on the buffer layer 108 by chemical vapor deposition method. Next, a second dielectric layer 114 is deposited on the first electrode 112, wherein the second dielectric layer 114 comprises a silicon nitride layer with thickness of about 30 angstroms and a silicon oxide layer with thickness of about 130 angstroms thereon. Then, a second electrode 116 of the capacitor is formed on the second dielectric layer 114. The thickness of the second electrode 116 is thicker than the first electrode 112 as shown in FIG. 2.
Therefore, a capacitor structure composes of the first electrode 112, the second dielectric layer 114, and the second electrode 116. Thereafter, as a key feature of the conventional metal via antifuse process, a third dielectric layer 118 such as silicon dioxide layer is deposited on the second electrode 116 by CVD method. Then, referring to FIG. 3, a photoresist layer (not shown) with an antifuse via pattern is formed on the third dielectric layer 118 by alignment process. Next, an etching process is performed to form an antifuse via open 120 in the third dielectric layer 118. Then, a second conductive wire 122 is deposited to fill the antifuse via open 120 and on the third dielectric layer 118.
The disadvantage for the conventional antifuse via structure is that the large capacitor area with lager capacitance, due to the first conductive layer is deposited to fill the tungsten keyhole such that the device processes with lower speed. The capacitor area can be calculated by formula xcfx80*(D/2)2, wherein the xcfx80 is 3.14, D is width of the second dielectric layer 114, herein the width value of the second dielectric layer 114 is of about 0.52 um. Therefore, according to the formula, we can obtain the values of flat capacitor area is 0.212 um2. Furthermore, another disadvantage is that the thin dielectric layer (second dielectric layer 114) is very difficult to control by plasma-enhanced chemical vapor deposition method especially for 0.15 um integrated circuit fabricating process.
It is an object of this invention to reduce the capacitance of the antifuse via structure.
It is another object of this invention to keep the thickness of the dielectric layer at the bottom of antifuse via such that the proper dielectric thickness of antifuse can be obtained.
It is still another object of this invention to utilize an intentionally misaligned process of antifuse via to the metal plug such that the breakdown can be occurred on the corner of metal plug to keep the same as the current antifuse.
According to abovementioned objects, the present invention provides a structure for improving the capacitance of the antifuse via structure. The antifuse via structure comprises a substrate having a first conductive wire therein, and a first dielectric layer having a conductive plug on the substrate. Then, a buffer layer is on the first dielectric layer and partial conductive plug. Next, a first conductive layer is on the buffer layer, wherein the first conductive layer used as first electrode of the capacitor. Then, a second dielectric layer is on the first electrode. Next, as another key feature of the present invention, an antifuse via open in the second dielectric layer such that the capacitor area is smaller than the conventional flat area. Then, a third dielectric layer is on the second dielectric layer and on sidewall of antifuse via open. Thereafter, a second electrode of capacitor is on the third dielectric layer. Then, a second conductive wire is on the top of the second electrode. The advantage of the present invention is that the dielectric thickness of antifuse at the bottom of antifuse via is much thinner than on the flat area. Therefore, the dielectric can be kept as thick as before, and proper the dielectric thickness of antifuse can be obtained by changing the antifuse via profile or aspect ratio.
Furthermore, the present invention provides a method for forming an antifuse via structure comprising a substrate having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer with a via pattern is formed on the first dielectric layer. Next, an etching process is performed to first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to remove portion of the first conductive layer to form a conductive plug. Next, a buffer layer is deposited on the partial first dielectric layer and on the conductive plug, and another polishing process is performed to remove the partial buffer layer on the conductive plug to expose partial conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer. Then, a second dielectric layer is deposited on the first electrode. Next, as a key step of the present invention, an intentionally misaligned process is performed to form an antifuse via open such that the breakdown will be occurred on the corner of the conductive plug. Thus, the current antifuse can be kept as before. The steps of forming antifuse via open include a photoresist layer is formed on the second dielectric layer by an intentionally misaligned process. Then, an etching process is performed to remove portion of the second dielectric layer to form an antifuse via open in second dielectric layer. After removing the photoresist layer, the third dielectric layer is deposited on second dielectric layer and on the sidewall of the antifuse via open. Next, a second electrode of the capacitor is deposited on the partial second dielectric layer. Thereafter, a second conductive wire is formed on the second electrode.
The advantage for the process of the present invention is that the capacitor area will be shrunk such that the capacitance can be diminished as low as ⅓ of the original data. Furthermore, the thickness shrinking of the dielectric layer in plasma-enhanced chemical vapor deposition method can be also easily performed for 0.15 um integrated circuit fabrication process.